1. Field of the Invention
The present invention relates to semiconductor integrated circuit verification methods and test pattern preparation methods for verifying and testing semiconductor integrated circuits.
2. Conventional Technique
Before shipped as products, LSIs are tested whether their inner circuits function properly. Such a test is carried out by inputting a test pattern into the LSI using a test apparatus (i.e., an LSI tester). In order to perform the test in a stable manner, verification has to be performed sufficiently so that the test pattern becomes a test pattern in which variation in the LSI process, temperature, voltage and the like, and constraints of the test apparatus are considered.
There are two verification methods: dynamic logic verification and static logic verification. Dynamic logic verification is a method in which a circuit to be verified is made to operate and operation by each of the sections in the circuit is verified. Static logic verification is a method for verifying the total value of signal delay times in the entire signal paths to be checked. Of these logic verification techniques, the dynamic logic verification has been the mainstream approach. However, this method takes an enormous amount of processing time to verify a recent miniaturized integrated circuit with higher density. Therefore, statistic verification has been replacing dynamic verification.
Hereinafter, a conventional semiconductor integrated circuit verification method will be briefly described with reference to the accompanying drawings.
FIG. 46 is a view illustrating an ordinary library used in a typical conventional semiconductor integrated circuit verification method. FIG. 47 is a view illustrating an ordinary library used in a semiconductor integrated circuit verification method according to a first conventional example. FIG. 48 is an explanatory timing chart indicating the semiconductor integrated circuit verification method of the first conventional example.
The semiconductor integrated circuit verification method of the first conventional example, which is a verification method developed in consideration of constraints of a test apparatus, is described in Japanese Laid-Open Publication No. 11-142489. In this verification method, a test stabilization library 1007 such as shown in FIG. 47 is used instead of an ordinary library 1001 such as shown in FIG. 46. The test stabilization library 1007 includes a signal propagation delay buffer 1003 and a signal-propagation/transient-response-delay buffer 1005.
A shown in FIG. 48, an output signal, which is output from a semiconductor integrated circuit in response to an input signal, is in a transition state when the signal rises from the low level (hereinafter simply referred to as the “L level”) to the high level (hereinafter simply referred to as the “H level”) or falls from the H level to the L level. In the transition state, the signal is neither at the H level nor at the L level. This transition state, in which the signal is neither at the H level nor at the L level, includes a transition state in which the signal is when it rises or falls, a Z state (i.e., a high impedance state), and an intermediate (resistive) state between the H level and the L level.
A verification apparatus used in the first conventional example is furnished with a storage section for storing output-signal expected values derived from circuit information. The expected values are compared with measurement-system determination results, which are measurement results, by a dedicated verification tool, for example. However, if the comparison is performed when the output signal is at the Z level, the measurement of the signal becomes unstable, leading to an inaccurate test.
In the verification method of the first conventional example, an output IN1 from the signal propagation delay buffer 1003 changes from the L level to the H level and from the H level to the L level at the rising and falling times of the output signal, respectively. An output IN2 from the signal-propagation/transient-response-delay buffer 1005 changes from the L level to the H level or from the H level to the L level at the point in time when the voltage of the output signal reaches the H-level threshold voltage. This permits a strobe point to be set in a period of time other than the periods of time in which the output signal is in the Z state, thereby enabling an accurate test.
Japanese Laid-Open Publication No. 2001-235522 discloses a second conventional example which is a test pattern preparation method in which static timing analysis is used.
FIG. 49 is a flowchart schematically indicating the test pattern preparation method according to the second conventional example.
As shown in FIG. 49, this method indicates a method for preparing a test vector used in a verification method which includes statistic timing analysis.
First, a test-vector-preparation supporting section 1015 prepares a test-data-extraction-timing designating file 1017 which includes timing conditions. The test-vector-preparation supporting section 1015 also prepares a test-vector-timing designating file 1016.
Next, the test-data-extraction-timing designating file 1017 is input into a logic simulation section 1018. The logic simulation section 1018 then performs dynamic verification using the test-data-extraction-timing designating file 1017 and a test-vector generation program 1020, thereby preparing a final test vector 1021.